Publications

Subthreshold and Gate-Leakage

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2003
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits, Rahul M Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown, International Conference on Computer Aided Design (ICCAD'03), San Jose, CA, pp. 689-692, November 9-13, 2003.
Standby Currents in PD-SOI Pseudo-nMos  Circuits,  Jay Sivagnaname, Richard B. Brown, IEEE International SOI Conference, Newport Beach, CA, pp. 95-96, September 29-October 2, 2003.
Noise Consideration and Detailed Comparison of Low Standby Gate/Sub-Threshold Leakage Digital Circuits in Nano-Scale SOI Technology, Koushik Das, Rajiv Joshi, Ching-Te Chuang and Richard Brown, IEEE International SOI Conference, Newport Beach, CA, pp. 87-88, September 29-October 2, 2003.

New Digital Circuit Techniques for Total Standby Leakage Reduction in Nano-Scale SOI Technology, Koushik Das, Rajiv V. Joshi, Ching-Te Kent Chuang, Peter W. Cook, Richard B. Brown, European Solid-State Circuits Conference (ESSCIRC 2003), Lisbon, Portugal, September 16-18, 2003, to be published.

Circuit Techniques for Gate and Sub-Threshold Leakage Minimization in Future CMOS Technologies, Rahul Rao, Jeffrey Burns, and Richard Brown, European Solid-State Circuits Conference (ESSCIRC 2003), Lisbon, Portugal, September 16-18, 2003, to be published.

Efficient Techniques for Gate Leakage Estimation, Rahul M. Rao, Jeffrey Burns, Anirudh Devgan, and Richard B. Brown, Int. Symposium on Low Power Electronics and Design (ISLPED'03), Seoul, Korea, pp. 100-103, August 25-27, 2003.

New Optimal Design Strategies and Analysis of Ultra-Low Leakage Circuits for Nano-Scale SOI Technology, Koushik Das, Rajiv V. Joshi, Ching-Te Kent Chuang, Peter W. Cook, and Richard B. Brown, Int. Symposium on Low Power Electronics and Design (ISLPED'03), Seoul, Korea, pp. 168-171, August 25-27, 2003.