Publications: SOI

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2004
A Body-Driven Offset Cancellation Technique in PD-SOI, Fadi Gebara, Steven Martin, Keith Kraver, Richard B. Brown, 24th Int. Conference on Microelectronics (MIEL 2004), May 16-19, 2004, Nis, Serbia and Montenegro, to be published.
2003
Effect of Scaling on Stand-by Current in PD-SOI Pseudo-nMOS Circuits, Jayakumaran Sivagnaname, Richard B. Brown, The 46th IEEE Midwest Symposium on Circuits and Systems, Cairo, Egypt, Dec. 27-30, 2003, to be published.
Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13µm PD-SOI, Alan J. Drake, Kevin J. Nowka, Richard B. Brown," IFIP VLSI-SoC International Conference 2003, Darmstadt, Germany, pp. 363-368, December 1-3, 2003.
Analysis of the Impact of Gate-Body Signal Phase on DTMOS Inverters in 0.13µm PD-SOI, Alan J. Drake, Noah Zamdmer, Kevin J. Nowka, and Richard B. Brown,  IEEE International SOI Conference, Newport Beach, CA, pp. 99-100, September 29-October 2, 2003.
Noise Consideration and Detailed Comparison of Low Standby Gate/Sub-Threshold Leakage Digital Circuits in Nano-Scale SOI Technology, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang and Richard B. Brown, IEEE International SOI Conference, Newport Beach, CA, pp. 87-88, September 29-October 2, 2003.
New Digital Circuit Techniques for Total Standby Leakage Reduction in Nano-Scale SOI Technology, Koushik Das, Rajiv V. Joshi, Ching-Te Kent Chuang, Peter W. Cook, Richard B. Brown, European Solid-State Circuits Conference (ESSCIRC 2003), Lisbon, Portugal, September 16-18,  2003.

Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS, Koushik Das and Richard Brown, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), Tampa, Florida, pp. 29-34, Feb. 20-21, 2003.
Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for PD-SOI CMOS Technolology, Koushik Das and Richard Brown,  Proceedings of the 2003 IEEE International Conference on VLSI Design, New Delhi, India, pp. 291-296, January 4-8, 2003.
2002
Novel Ultra Low-Leakage Power Circuit Techniques and Design Algorithms in PD-SOI for Sub-1 V Applications, Proceedings of the  2002 IEEE International SOI Conference, Williamsburg, VA, pp. 88-90, October 7-10, 2002.
A Novel Sub-1 V High Speed Circuit Design Technique in Partially Depleted SOI-CMOS Technology with Ultra Low-Leakage Power, Koushik Das and Richard Brown, Proceedings of the 2002 European Solid-State Circuits Conference (ESSCIRC 2002), Florence, Italy, pp. 267-270, September 24-26, 2002.
2001
Circuit Style Comparison based on the Variable Voltage Transfer Characteristic and Floating b Ratio Concept of Partially Depleted SOI, Koushik K. Das and Richard B. Brown, 2001 IEEE International SOI Conference, Durango, CO, pp. 103-104, October 1-4, 2001.

Analysis of the Floating Voltage Transfer Characteristic and Comparison of Circuit Styles in Partially Depleted SOI-CMOS, Koushik K. Das and  Richard B. Brown, 27th European Solid-State Circuits Conference, Villach, Austria,  pp. 388-391, September 2001.
2000
Evaluation of Circuit Approaches in PD-SOI CMOS, Koushik Das and Richard Brown, in Proceedings of the 2000 IEEE International SOI Conference, Wakefield, MA, pp. 98-99, October 2-5, 2000.
Evaluation of Circuit Design Approaches in Partially Depleted SOI-CMOS Using a 32-bit PowerPC Design Vehicle," Koushik K. Das and Richard B. Brown, TechCon 2000, Sept. 21-23, 2000.