Richard B. Brown - Research
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Low Power SOl PowerPC FXU
Graduate Student Researchers: Jayakumaran Sivagnaname, Rahul Rao

A Dual Issue POWERPC FXU designed in 0.18µm bulk CMOS. This processor will be used as a design vehicle and remapped to SOl to illus­trate the applicability of novel SOI low power design techniques.

SOI technology has extended CMOS performance at smaller dimensions by minimizing short-channel effects, reducing junction capacitances, and providing latch-up immunity in addition to providing performance benefits. This project aims to optimize digital circuits for power and performance by exploiting the inherent benefits of the SOI technology. A 32-bit PowerPC fixed-point execution unit (FXU) has been designed as a test vehicle for SOI digital circuits. This work will proceed by examining the modules of this FXU in view of Partially Depleted SOI (PD-SOI) characteristics. These modules will be redesigned to exploit SOI merits while mitigating the history effect, the parasitic bipolar effect, and other SOI demerits. Techniques intended for low power SOI design will be presented and implemented. Leakage mitigation techniques and tools for leakage analysis will be developed. The eventual objective is to design and fabricate a low power SOI POWERPC FXU. Funding has been provided by AMD (Advanced Micro Devices) under the Semiconductor Research Corporation (SRC) Task ID 770.001.