Richard B. Brown - Research
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Robust Low Power Digital Circuit Design in Partially Depleted SOl
PhD Graduate in 2003: Koushik K. Das

This is a test circuit layout for validation of our low-leakage power circuit techniques. The circuits are in the process of being fabricated in an advanced IBM PD-SOI process.

The goal of this research project is to develop robust low-leakage power digital circuit techniques in SOl technology. Traditionally, supply voltage has been scaled along with technology to keep power density within manageable limits. The threshold voltage has been simultaneously reduced to maintain speed. However, because of the exponential relationship between leakage current and threshold voltage in the weak inversion mode of a transistor, leakage power becomes significant at low threshold voltages, and needs to be effectively con­trolled. With the gate oxide thickness being reduced to a few nanometers, gate-to­-body tunneling leakage is also a cause of concern for modern chip designers. This project aims at devising novel circuit schemes for standby power reduction in par­tially depleted SOl technology.

SOl technology has some non-ideal characteristics which make reliable circuit design challenging. These characteristics include the parasitic bipolar effect and the history effect. This project is aimed at addressing these issues and coming up with robust low-power design methodologies for PD-SOI. Funding provided by the Semiconductor Research Corporation.