Richard B. Brown - Research
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Distributed Capacitance LC Clock Generation
Graduate Student Researcher: Alan J. Drake

Distributed LC circuit, The inductors and transistors of the VCO can be seen at the left. The inductors are 1000µm long and 50µm wide. The capacitance loading the VCO is the clock distribution network of the scanchain on the right.

While the power efficiency of succeeding process generations has improved, increased operating frequencies, integration levels, and leakage currents are tax­ing the power budgets of high-performance VLSI designs. In the current generation of microprocessors that includes the Power4 and Pentium4, more than 50% of their power is dissipated in the clock tree. Newer process generations that include copper metals, low-K dielectrics, and SOl substrates are making integrated inductors possible. In this project, an on-chip VCO is designed where the capacitance of the VCO is composed of the gates and wires of the clock distribu­tion network. If a high enough quality-factor can be achieved in the VCO, the cir­cuit will resonate the clock power between the gates and the inductors, achieving substantial power savings. A test circuit was built that implements a 24x64 bit scanchain clocked by the resonant circuit. Preliminary tests show that the reso­nant driven clock network designed dissipates one half the power of a standard, buffer driven clock network. Further studies are being pursued to exam the qual­ity and stability of resonant clocks as well as the effects of a sinusoidal clock on digital logic. This project is funded by the IBM Austin Center for Advanced Studies.