This project is intended to develop and implement a digital core that executes the Continuous Interleaved Sampling (CIS) algorithm for a Cochlear Implant (CI). Figure 1 shows a schematic diagram of the CIS algorithm. This core will be instituted as part of the WIMS Microcontroller (see Project Description "Micropower Digital SOI") and integrated as part of the system architecture for the neural prosthesis testbed.

This architecture is intended to have several programmable features in order to achieve the same variability for patient specific parameters as present day commercial implants. However, designing a custom architecture tuned specifically for this sound processing algorithm will hopefully be a lower power implementation than using a software programmable DSP chip as part of the system. Comparisons will be done to other existing implementations.