Richard B. Brown - Research
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Improving the Performance of Standard Cell Designs and Libraries
Graduate Student Researcher: Matthew R. Guthaus

Standard cell and full custom design methodologies have a significant performance gap and require drastically different amounts of design effort. This project describes how a standard cell design methodology can be improved by automating some concepts used in full custom design.  Cell library synthesis and transistor sizing are integrated to allow standard cell libraries to be automatically customized. The resulting designs use cells with transistor sizes optimized for power and delay while using an automatically placed and routed design style. 

 Continuous, analytic gate-sizing algorithms allow the fast location of a global minimum solution, but require a mapping from continuous cell sizes to a fixed set of library cells.  A gain-based, fixed-delay sizer has been implemented that can run on large designs very quickly. Heuristics have been implemented to select the best new cells to supplement the library based on power, frequency of usage, and the continuously sized solution.  Preliminary results on benchmarks show up to 30% power savings without affecting delay by adding only a few carefully selected cell sizes.  This research was funded by DARPA through BAE Systems, Government Contract Number: F33615-01-C-1910.