Richard B. Brown - Research
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A 900 mV Analog Front End for Low Power Mixed­ Signal Applications
Graduate Student Researchers: Keith L. Kraver, Fadi H. Gebara 

Die photo of the fabricated AFE in TSMC 0.18μm CMOS process. Layout contains buffers, programmable amplifiers. analog to digital converters, digital filters, and current references. Die is ~2mm x 2mm.

In this project, low-voltage, low-power analog and mixed-signal circuits are integrated with a digital process to implement an analog front end (AFE) for single chip instrumentation. This AFE has been fabricated through the MOSIS service in the 0.18 μm TSMC process. The AFE contains input voltage buffers, a programmable gain amplifier (PGA), a second order delta-sigma analog-to-digital converter (ADC), and a third-order digital comb filter. Switched-capacitor circuits are employed exclusively in the AFE due to their superior low voltage, low power performance and robustness. The threshold voltages of the transistors are large in comparison to the 900 mV supply. This is especially apparent when using a MOS device as a switch near the mid rail point (450 mV) where the conductance of the transistors falls nearly to zero, making the switch unusable. The effect of the low conductance is translated into reduced dynamic range of the ADC. Three tech­niques (clock doubling, switched opamps, and body biased switches) have been developed to overcome this problem. Each technique has been evaluated in simulation as well as in silicon. This project is funded by the Engineering Research Centers Program of the National Science Foundation under Award Number EEC-­9986866.